ADSP-BF534 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF534' PDF : 68 Pages View PDF
Serial Peripheral Interface Port—Slave Timing
Table 29 and Figure 23 describe SPI port slave operations.
Table 29. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
tSPICHS
Serial Clock High Period
tSPICLS
Serial Clock Low Period
tSPICLK
Serial Clock Period
tHDS
Last SCK Edge to SPISS Not Asserted
tSPITDS
Sequential Transfer Delay
tSDSCI
SPISS Assertion to First SCK Edge
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
tHSPID
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
tDSOE
tDSDHI
tDDSPID
tHDSPID
SPISS Assertion to Data Out Active
SPISS Deassertion to Data High Impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
ADSP-BF534/ADSP-BF536/ADSP-BF537
Min
Max
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
1.6
1.6
0
8
0
8
0
10
0
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPISS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
MISO
(OUTPUT)
tSPICHS
tSPICLS
tSDSCI
tSPICLS
tSPICHS
tDSOE
tDDSPID
tHDSPID
MSB
CPHA = 1
MOSI
(INPUT)
tSSPID
tHSPID
MSB VALID
tDSOE
tDDSPID
MISO
(OUTPUT)
MSB
CPHA = 0
MOSI
(INPUT)
MSB VALID
tSPICLK
tHDS
tSPITDS
tDDSPID
tSSPID
tDSDHI
LSB
tHSPID
LSB VALID
tDSDHI
LSB
tSSPID
tHSPID
LSB VALID
Figure 23. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. B | Page 41 of 68 | July 2006
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