ADSP-BF534 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF534' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 38. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter1, 2
Min
Max
Unit
tECOLH
COL Pulse Width High
tETxCLK × 1.5
ns
tERxCLK × 1.5
tECOLL
tECRSH
tECRSL
COL Pulse Width Low
CRS Pulse Width High
CRS Pulse Width Low
tETxCLK × 1.5
ns
tERxCLK × 1.5
tETxCLK × 1.5
ns
tETxCLK × 1.5
ns
1 MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2 The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
Table 39. 10/100 Ethernet MAC Controller Timing: MII Station Management
Parameter1
Min
Max
Unit
tMDIOS
tMDCIH
tMDCOV
tMDCOH
MDIO Input Valid to MDC Rising Edge (Setup)
MDC Rising Edge to MDIO Input Invalid (Hold)
MDC Falling Edge to MDIO Output Valid
MDC Falling Edge to MDIO Output Invalid (Hold)
10
ns
10
ns
25
ns
–1
ns
1 MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
of the system clock SCLK. MDIO is a bidirectional data line.
ERxCLK
tERXCLKW
tERXC LK
ERxD3-0
ERxDV
ERxER
MII TxCLK
ETxD3-0
ETxEN
tERXCLKIS
tERXCLKIH
Figure 29. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
tETXCLKW
tETXCLK
tETXCLKOH
tETXCLKOV
Figure 30. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Rev. B | Page 48 of 68 | July 2006
Share Link: 
