
ADSP-BF534/ADSP-BF536/ADSP-BF537
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
DATA
SAMPLING/
FRAME
SYNC
SAMPLING
EDGE
DATA
SAMPLING/
FRAME
SYNC
SAMPLING
EDGE
tSFSPE
tHFSPE
tSDRPE
tHDRPE
Figure 16. PPI GP Rx Mode with External Frame Sync Timing
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
DATA
DRIVING/
FRAME
SYNC
DRIVING
EDGE
tHOFSPE
tDFSPE
DATA
DRIVING/
FRAME
SYNC
DRIVING
EDGE
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
tDDTPE
tHDTPE
Figure 17. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. B | Page 34 of 68 | July 2006