ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 27. External Late Frame Sync
Parameter
Switching Characteristics
tDDTLFSE
tDTENLFS
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2
Data Enable from Late FS or MCE = 1, MFD = 01, 2
1 MCE = 1, TFS enable and TFS valid follow tDDTENFS and tDDTLFS.
2 If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply.
Min
0
Max
10.0
Unit
ns
ns
DATA RECEIVE-INTERNAL CLOCK
DRIVE
EDGE
tSCLKIW
RSCLK
tHOFSE
tDFSE
tSFSI
RFS
SAMPLE
EDGE
tHFSI
DATA RECEIVE-EXTERNAL CLOCK
DRIVE
EDGE
tSCLKEW
SAMPLE
EDGE
RSCLK
tHOFSE
tDFSE
tSFSE
RFS
tSDRI
tHDRI
tSDRE
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT-INTERNAL CLOCK
DRIVE
EDGE
tSCLKIW
SAMPLE
EDGE
TSCLK
tHOFSI
tDFSI
tSFSI
TFS
tHDTI
tDDTI
DT
tHFSI
DATA TRANSMIT-EXTERNAL CLOCK
DRIVE
EDGE
tSCLKEW
TSCLK
tHOFSE
tDFSE
tSFSE
SAMPLE
EDGE
TFS
tHDTE
tDDTE
DT
TSCLK (EXT.)
TFS (“LATE,” EXT.)
DT
TSCLK (INT.)
TFS (“LATE,” INT.)
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
tDDTENE
TSCLK/RSCLK
tDDTTE
DRIVE
EDGE
tDDTENI
TSCLK/RSCLK
DRIVE
EDGE
tDDTTI
tHFSE
tH DRE
tHFSE
Figure 19. Serial Ports
Rev. B | Page 37 of 68 | July 2006