ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 16. System Clock Requirements
Parameter
fSCLK
fSCLK
fSCLK
fSCLK
Condition
VDDEXT = 3.3 V, VDDINT ≥ 1.14 V
VDDEXT = 3.3 V, VDDINT < 1.14 V
VDDEXT = 2.5 V, VDDINT ≥ 1.14 V
VDDEXT = 2.5 V, VDDINT < 1.14 V
Min
Max
Unit
133
MHz
100
MHz
133
MHz
100
MHz
Table 17. Clock Input and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
tCKINL
tCKINH
tBUFDLAY
tWRST
CLKIN Period1
CLKIN Low Pulse2
CLKIN High Pulse2
CLKIN to CLKBUF Delay
RESET Asserted Pulse Width Low3
25.0
100.0
ns
10.0
ns
10.0
ns
10
ns
11 tCKIN
ns
1 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 12 through Table 16. Since
by default the PLL is multiplying the CLKIN frequency by 10, 300 MHz and 400 MHz speed grade parts can not use the full CLKIN period range.
2 Applies to bypass mode and nonbypass mode.
3 Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
CLKIN
tCKIN
tCKINL
tCKINH
CLKBUF
tBUFDLAY
tBUFDLAY
RESET
tWRST
Figure 9. Clock and Reset Timing
Rev. B | Page 27 of 68 | July 2006