ADSP-BF538F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF538F' PDF : 56 Pages View PDF
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 22. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter
Timing Requirements
tWBR
BR Pulsewidth
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
tSE
CLKOUT Low to xMS, Address, and RD/WR enable
tDBG
CLKOUT High to BG High Setup
tEBG
CLKOUT High to BG Deasserted Hold Time
tDBH
CLKOUT High to BGH High Setup
tEBH
CLKOUT High to BGH Deasserted Hold Time
Min
2 x tSCLK
Max
4.5
4.5
3.6
3.6
3.6
3.6
Unit
ns
ns
ns
ns
ns
ns
ns
CLKOUT
BR
AMSx
ADDR19-1
ABE1-0
AWE
ARE
BG
BGH
tWBR
tSD
tSE
tSD
tSE
tSD
tSE
tDBG
tEBG
tDBH
tEBH
Figure 17. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Rev. PrD | Page 31 of 56 | May 2006
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