ADSP-BF538F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF538F' PDF : 56 Pages View PDF
ADSP-BF538/ADSP-BF538F
Preliminary Technical Data
Table 27. External Late Frame Sync
Parameter
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2
tDTENLFS
Data Enable from late FS or MCE = 1, MFD = 01, 2
1 MCE = 1, TFS enable and TFS valid follow tDTENLFS and tDDTLFSE.
2 If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
Min
0
Max
Unit
10.0
ns
ns
DATA RECEIVE- INTERNAL CLOCK
DRIVE
EDGE
tSCLKIW
RSCLK
tHOFSE
tDFSE
tSFSI
RFS
SAMPLE
EDGE
tHFSI
DATA RECEIVE- EXTERNAL CLOCK
DRIVE
EDGE
tSCLKEW
SAMPLE
EDGE
RSCLK
tHOFSE
tDFSE
tSFSE
RFS
tSDRI
tHDRI
tSDRE
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT- INTERNAL CLOCK
DRIVE
EDGE
tSCLKIW
SAMPLE
EDGE
TSCLK
tHOFSI
tDFSI
tSFSI
TFS
tHDTI
tDDTI
DT
tHFSI
DATA TRANSMIT- EXTERNAL CLOCK
DRIVE
EDGE
tSCLKEW
TSCLK
tHOFSE
tDFSE
tSFSE
SAMPLE
EDGE
TFS
tHDTE
tDDTE
DT
TSCLK (EXT)
TFS ("LATE", EXT.)
DT
TSCLK (INT)
TFS ("LATE", INT.)
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
tDT EN E
TSCLK / RSCLK
tDDTTE
DRIVE
EDGE
tDTENI
TSCLK / RSCLK
DRIVE
EDGE
tDDTTI
tHFSE
tHDR E
tHFSE
Figure 22. Serial Ports
Rev. PrD | Page 36 of 56 | May 2006
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