ADSP-BF538F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF538F' PDF : 56 Pages View PDF
ADSP-BF538/ADSP-BF538F
Serial Peripheral Interface Port—Slave Timing
Table 29 and Figure 26 describe SPI port slave operations.
Table 29. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
tSPICHS
Serial Clock High Period
tSPICLS
Serial Clock low Period
tSPICLK
Serial Clock Period
tHDS
Last SCK Edge to SPI0SS Not Asserted
tSPITDS
Sequential Transfer Delay
tSDSCI
SPI0SS Assertion to First SCK Edge
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
tHSPID
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
tDSOE
tDSDHI
tDDSPID
tHDSPID
SPI0SS Assertion to Data Out Active
SPI0SS Deassertion to Data High impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
Preliminary Technical Data
Min
Max
2tSCLK – 1.5
2tSCLK – 1.5
4tSCLK – 1.5
2tSCLK – 1.5
2tSCLK – 1.5
2tSCLK – 1.5
1.6
1.6
0
8
0
8
0
10
0
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPISS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
MISO
(OUTPUT)
tSPICHS
tSPICLS
tSDSCI
tSPICLS
tSPICHS
tDSOE
tDDSPID
tHDSPID
MSB
CPHA=1
MOSI
(INPUT)
tSSPID
tHSPID
MSB VALID
tDSOE
tDDSPID
MISO
(OUTPUT)
MSB
CPHA=0
MOSI
(INPUT)
MSB VALID
tSPICLK
tHDS
tSPITDS
tDDSPID
tSSPID
tDSDHI
LSB
tHSPID
LSB VALID
tDSDHI
tSSPID
LSB
tHSPID
LSB VALID
Figure 26. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. PrD | Page 40 of 56 | May 2006
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