
Preliminary Technical Data
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
DATA0 IS
SAMPLED
FRAME
SYNC IS
SAMPLED
FOR
DATA0
DATA1 IS
SAMPLED
tSFSPE
tHFSPE
ADSP-BF538/ADSP-BF538F
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
tSDRPE tHDRPE
Figure 19. PPI GP Rx Mode with External Frame Sync Timing
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
FRAME
SYNC IS
SAMPLED
DATA0 IS
DRIVEN
OUT
tSFSPE
tHFSPE
tHDTPE
DATA0
tDDTPE
Figure 20. PPI GP Tx Mode with External Frame Sync Timing
Rev. PrD | Page 33 of 56 | May 2006