AT90PWM81 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT90PWM81' PDF : 325 Pages View PDF
AT90PWM81/161
5.2.5
External Clock
To drive the device from this external clock source, CLKI should be driven as shown in Figure 5-
3. To run the device on an external clock, the CKSEL Fuses or CSEL field must be programmed
as shown in Table 5-1 on page 28.
Figure 5-3. External clock drive configuration.
External
Clock
Signal
CLKI
(XTAL1)
GND
5.2.6 PLL
When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT
field as shown in Table 5-8.
Table 5-8. Start-up times for the external clock selection.
SUT1..0 (1)
CSUT1..0 (2)
Start-up time from
power-down
Additional delay from reset
Recommended usage
00
6CK
14CK
BOD enabled
01
6CK
14CK + 4ms
Fast rising power
10
6CK
14CK + 64ms
Slowly rising power
11
Reserved
Notes: 1. Flash Fuse bits.
2. CLKSELR register bits.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
39 for details.
To generate high frequency and accurate PWM waveforms, the ‘PSC’s need high frequency
clock input. This clock is generated by a PLL. To keep all PWM accuracy, the frequency factor of
PLL must be configured by software.
The internal PLL in AT90PWM81/161 generates a clock frequency multiplied from nominally
8MHz input. The source of the 8MHz PLL input clock can be selected from three possible
sources (see the Figure 5-4 on page 34):
• Internal RC Oscillator
• Crystal oscillator
• External clock
The internal PLL is enabled only when the PLLE bit in the register PLLCSR is set. The bit
PLOCK from the register PLLCSR is set when PLL is locked.
When selected as clock source by fuse, the PLL multiplication factor is initialized at the value of
6, compatible with a 3V supply.
33
7734Q–AVR–02/12
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