AT90PWM81 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT90PWM81' PDF : 325 Pages View PDF
AT90PWM81/161
The PLL is locked on the source oscillator which must remains close to 8MHz to assure proper
lock of the PLL.
Both internal RC Oscillator and PLL are switched off in Power-down and Standby sleep modes
Table 5-9.
CKSEL3..0
0100
0101
0001
Start-up times when the PLL is selected as system clock.
SUT1..0
00
Start-up time from power-
down
1K CK
Additional delay from reset
(VCC = 5.0V)
14CK
01
1K CK
14CK + 4ms
10
1K CK
14CK + 64ms
11
16K CK
14CK
00
16K CK
14CK
01
16K CK
14CK + 4ms
10
16K CK
14CK + 4ms
11
16K CK
14CK + 64ms
00
1K CK
14CK
01
1K CK
14CK + 4ms
10
1K CK
14CK + 64ms
Clock source
External crystal or
resonator
External clock
Internal RC oscillator
Figure 5-4.
PCK clocking system.
OSCCAL
CKSEL3..0
PLLE PLLF3..0
Lock
Detector
PLOCK
RC OSCILLATOR
8MHz
XTAL1
XTAL2
OSCILLATORS
PLL
*N
DIVIDE
BY 4
CLK PLL
CK SOURCE
5.2.7
Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse or COUT bit of CLKSELR register has to be programmed. This mode is suitable when the
chip clock is used to drive other circuits on the system. Note that the clock will not be output dur-
ing reset and the normal operation of I/O pin will be overridden when the fuses are programmed.
Any clock source can be selected when the clock is output on CLKO. If the System Clock Pres-
caler is used, it is the divided system clock that is output.
34
7734Q–AVR–02/12
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