AT91M40400 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91M40400' PDF : 116 Pages View PDF
WD: Watchdog Timer
The AT91M40400 has an internal watchdog timer which
can be used to prevent system lock-up if the software
becomes trapped in a deadlock. In normal operation the
user reloads the watchdog at regular intervals before the
timer overflow occurs. If an overflow does occur, the watch-
dog timer generates one or a combination of the following
signals, depending on the parameters in WD_OMR (Over-
flow Mode Register):
• If RSTEN is set, an internal reset is generated
(WD_RESET as shown in Figure 46). See also
Watchdog Reset on page 8.
• If IRQEN is set, a pulse is generated on the signal
WDIRQ which is connected to the Advanced Interrupt
Controller
• If EXTEN is set, a low level is driven on the NWDOVF
signal for a duration of 8 MCKI cycles.
Figure 46. Watchdog Timer Block Diagram
The watchdog timer has a 16-bit down counter. Bits 12-15
of the value loaded when the watchdog is restarted are pro-
grammable using the HPVC parameter in WD_CMR (Clock
Mode). Four clock sources are available to the watchdog
counter: MCKI/8, MCKI/32, MCKI/128 or MCKI/1024. The
selection is made using the WDCLKS parameter in
WD_CMR. This provides a programmable time-out period
of 1ms to 2s with a 33 MHz system clock.
All write accesses are protected by control access keys to
help prevent corruption of the watchdog should an error
condition occur. To update the contents of the mode and
control registers it is necessary to write the correct bit pat-
tern to the control access key bits at the same time as the
control bits are written (the same write access).
Advanced
Peripheral
Bus (APB)
WD_RESET
WDIRQ
Control Logic
Overflow
NWDOVF
MCKI/8
MCKI/32
MCKI/128
MCKI/1024
Clock Select
Clear
CLK_CNT
16-Bit
Programmable
Down Counter
WD User Interface
WD Base Address: 0xFFFF8000
Table 12. WD Memory Map
Offset
Register
0x00
Overflow Mode Register
0x04
Clock Mode Register
0x08
Control Register
0x0C
Status Register
Name
WD_OMR
WD_CMR
WD_CR
WD_SR
Access
Read/Write
Read/Write
Write only
Read only
Reset State
0
0
---
0
106
AT91M40400
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