Timer/Counter1 – TCNT1H
and TCNT1L
Bit
Read/Write
Initial Value
7
R/W
0
6
5
4
3
2
1
0
TCNT1[15:8]
TCNT1H
TCNT1[7:0]
TCNT1L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Timer/Counter3 – TCNT3H
and TCNT3L
Bit
Read/Write
Initial Value
7
R/W
0
6
5
4
3
2
1
0
TCNT3[15:8]
TCNT3H
TCNT3[7:0]
TCNT3L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit tempo-
rary High Byte Register (TEMP). This Temporary Register is shared by all the other 16-
bit registers. See “Accessing 16-bit Registers” on page 114.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing
a compare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following
timer clock for all compare units.
Output Compare Register 1 A
– OCR1AH and OCR1AL
Bit
7
6
5
4
3
2
1
0
OCR1A[15:8]
OCR1AH
OCR1A[7:0]
OCR1AL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Output Compare Register 1 B
– OCR1BH and OCR1BL
Bit
7
6
5
4
3
2
1
0
OCR1B[15:8]
OCR1BH
OCR1B[7:0]
OCR1BL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Output Compare Register 1 C
– OCR1CH and OCR1CL
Bit
7
6
5
4
3
2
1
0
OCR1C[15:8]
OCR1CH
OCR1C[7:0]
OCR1CL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Output Compare Register 3 A
– OCR3AH and OCR3AL
Bit
7
6
5
4
3
2
1
0
OCR3A[15:8]
OCR3AH
OCR3A[7:0]
OCR3AL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
138 ATmega128
2467O–AVR–10/06