ATEMGA128-16AI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATEMGA128-16AI' PDF : 395 Pages View PDF
ATmega128
Output Compare Register 3 B
– OCR3BH and OCR3BL
Bit
7
6
5
4
3
2
1
0
OCR3B[15:8]
OCR3BH
OCR3B[7:0]
OCR3BL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Output Compare Register 3 C
– OCR3CH and OCR3CL
Bit
Read/Write
Initial Value
7
R/W
0
6
5
4
3
2
1
0
OCR3C[15:8]
OCR3CH
OCR3C[7:0]
OCR3CL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared
with the counter value (TCNTn). A match can be used to generate an output compare
interrupt, or to generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is
performed using an 8-bit temporary High Byte Register (TEMP). This Temporary Regis-
ter is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page
114.
Input Capture Register 1 –
ICR1H and ICR1L
Bit
Read/Write
Initial Value
7
R/W
0
6
5
4
3
2
1
0
ICR1[15:8]
ICR1H
ICR1[7:0]
ICR1L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Input Capture Register 3 –
ICR3H and ICR3L
Bit
Read/Write
Initial Value
7
R/W
0
6
5
4
3
2
1
0
ICR3[15:8]
ICR3H
ICR3[7:0]
ICR3L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
The Input Capture is updated with the counter (TCNTn) value each time an event occurs
on the ICPn pin (or optionally on the Analog Comparator Output for Timer/Counter1).
The Input Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary High Byte Register (TEMP). This Temporary Register
is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 114.
2467O–AVR–10/06
139
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