ATEMGA128-16AI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATEMGA128-16AI' PDF : 395 Pages View PDF
Timer/Counter Interrupt Mask
Register – TIMSK
Bit
Read/Write
Initial Value
7
OCIE2
R/W
0
6
TOIE2
R/W
0
5
TICIE1
R/W
0
4
OCIE1A
R/W
0
3
OCIE1B
R/W
0
2
TOIE1
R/W
0
1
OCIE0
R/W
0
0
TOIE0
R/W
0
TIMSK
Note:
This register contains interrupt control bits for several Timer/Counters, but only Timer1
bits are described in this section. The remaining bits are described in their respective
timer sections.
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The
corresponding interrupt vector (See “Interrupts” on page 59.) is executed when the ICF1
flag, located in TIFR, is set.
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare A Match Interrupt is enabled. The
corresponding interrupt vector (see “Interrupts” on page 59) is executed when the
OCF1A flag, located in TIFR, is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare B Match Interrupt is enabled. The
corresponding interrupt vector (see “Interrupts” on page 59) is executed when the
OCF1B flag, located in TIFR, is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding
interrupt vector (see “Interrupts” on page 59) is executed when the TOV1 flag, located in
TIFR, is set.
Extended Timer/Counter
Interrupt Mask Register –
ETIMSK
Bit
7
–
Read/Write
R
Initial Value
0
6
5
4
3
2
1
0
–
TICIE3 OCIE3A OCIE3B TOIE3 OCIE3C OCIE1C ETIMSK
R
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Note: This register is not available in ATmega103 compatibility mode.
• Bit 7:6 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices,
these bits must be set to zero when ETIMSK is written.
• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Input Capture Interrupt is enabled. The
corresponding interrupt vector (see “Interrupts” on page 59) is executed when the ICF3
flag, located in ETIFR, is set.
• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Output Compare A Match Interrupt is enabled. The
140 ATmega128
2467O–AVR–10/06
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