ATEMGA128L View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATEMGA128L' PDF : 395 Pages View PDF
Ports as General Digital
I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a
functional description of one I/O port pin, here generically called Pxn.
Figure 30. General Digital I/O(1)
Configuring the Pin
QD
DDxn
Q CLR
RESET
PUD
WDx
RDx
Pxn
QD
PORTxn
Q CLR
RESET
WPx
SLEEP
RRx
SYNCHRONIZER
DQ
LQ
DQ
PINxn
Q
RPx
clk I/O
PUD:
SLEEP:
clkI/O:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
WDx:
RDx:
WPx:
RRx:
RPx:
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports.
Each port pin consists of three Register bits: DDxn, PORTxn, and PINxn. As shown in
“Register Description for I/O Ports” on page 86, the DDxn bits are accessed at the DDRx
I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx
I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written
logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-
ured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up
resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic
zero or the pin has to be configured as an output pin. The port pins are tri-stated when a
Reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logic zero when the pin is configured as an out-
put pin, the port pin is driven low (zero).
66 ATmega128
2467O–AVR–10/06
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