ATEMGA128L View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATEMGA128L' PDF : 395 Pages View PDF
Reading the Pin Value
ATmega128
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} =
0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up
enabled state is fully acceptable, as a high-impedant environment will not notice the dif-
ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in
the SFIOR Register can be written to one to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 25 summarizes the control signals for the pin value.
Table 25. Port Pin Configurations
PUD
DDxn PORTxn (in SFIOR) I/O Pull-up Comment
0
0
X
Input
No Tri-state (Hi-Z)
0
1
Pxn will source current if ext. pulled
0
Input
Yes low.
0
1
1
Input
No Tri-state (Hi-Z)
1
0
X
Output No Output Low (Sink)
1
1
X
Output No Output High (Source)
Independent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register bit. As shown in Figure 30, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure
31 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min
respectively.
Figure 31. Synchronization when Reading an Externally Applied Pin Value
SYSTEM CLK
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
XXX
in r17, PINx
0x00
tpd, max
tpd, min
0xFF
67
2467O–AVR–10/06
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