ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
5.2 External Memory
The SAMA5D4 offers connection to a wide range of external memories or to parallel peripherals.
5.2.1
Supported Memories on DDR2/LPDDR/LPDDR2 Interface
16-bit or 32-bit external interface
512 Mbytes of address space on DDR CS and DDR/AES CS in 32-bit mode
256 Mbytes of address space on DDR CS and DDR/AES CS in 16-bit mode
Supports 16-bit or 32-bit 8-banks DDR2, LPDDR and LPDDR2 memories
Automatic drive level control
Multi-port
Dynamic scrambling
The port 0 of this interface has an embedded automatic AES encryption and decryption mechanism (refer to
Section 52. “Advanced Encryption Standard Bridge (AESB)”). Writing to or reading from the address
0x40000000 may trigger the encryption or decryption mechanism depending on the AESB on External
Memories configuration.
TrustZone: The multi-port feature of this interface implies TrustZone configuration constraints. Refer to
Section 15.12 “TrustZone Extension to AHB and APB” for more details.
5.2.2
Supported Memories on Static Memories and NAND Flash Interfaces
The Static Memory Controller is dedicated to interfacing external memory devices:
Asynchronous SRAM-like memories and parallel peripherals
NAND Flash (MLC and SLC) 8-bit data path
The Static Memory Controller is able to drive up to four chip selects. NCS3 is dedicated to the NAND Flash control.
The HSMC embeds the NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the
commands and address cycles to the NAND Flash and transferring the content of the page (for read and write) to
the NFC SRAM. It minimizes the CPU overhead.
In order to improve overall system performance, the DATA phase of the transfer can be DMA assisted. The static
memory embeds the NAND Flash Error Correcting Code Controller with the following features:
Algorithm based on BCH codes
Supports also SLC 1-bit (BCH 2-bit), SLC 4-bit (BCH 4-bit)
Programmable Error Correcting Capability
̶ 2-bit, 4-bit, 8-bit and 16-bit errors for 512 bytes/sector (4 Kbyte page)
̶ 24-bit error for 1024 bytes/sector (8 Kbyte page)
Programmable sector size: 512 bytes or 1024 bytes
Programmable number of sector per page: 1, 2, 4 or 8 blocks of data per page
Programmable spare area size
Supports spare area ECC protection
Supports 8-Kbyte page size using 1024 bytes/sector and 4-Kbyte page size using 512 bytes/sector
Error detection is interrupt driven
Provides hardware acceleration for error location
Finds roots of error-locator polynomial
Programmable number of roots
Dynamic scrambling
34 SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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