ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
Figure 7-1. System Controller Block Diagram
NRST
VDDBU
PIOBU[7..0]
fiq
secured_periph_irq[]
irq[23]
pmc_irq
irq
nonsecured_periph_irq[]
pit_irq
wdt_irq
dbgu_irq
MCK
periph_nreset
dbgu_rxd
MCK
Debug
periph_nreset
SLCK
Debug
Idle
proc_nreset
System Controller
VDDCORE Powered
Secured
Advanced
Interrupt
Controller
Advanced
Interrupt
Controller
Debug
Unit
Periodic
Interval
Timer
dbgu_irq
dbgu_txd
pit_irq
Watchdog
Timer
wdt_irq
wdt_fault
nfiq
fiq_vect
ptc_wakeup
nirq
irq_vect
por_ntrst
ntrst
proc_nreset
PCK
debug
Cortex A5
jtag_nreset
MCK
periph_nreset
Boundary Scan
TAP Controller
Bus Matrix
VDDCORE
POR
por_ntrst
jtag_nreset
Reset
Controller
periph_nreset
proc_nreset
backup_nreset
VDDBU
POR SLCK
SLCK
backup_nreset
MCK
12M PLL
32K RC
Real-Time
Clock
Secure Box Module
VDDBU Powered
rtc_irq
rtc_alarm
ntrst
irq[20]
irq[23]
wkup
SECURAM
8 KB
+
512 bits
UPLLCK
UHP48M
UHP12M
periph_nreset
periph_irq[50]
USB High Speed
Host Port
UPLLCK
periph_nreset
periph_irq[49]
USB High Speed
Device Port
SHDN
WKUP
XIN32
XOUT32
XIN
XOUT
PA0–PA31
PB0–PB31
PC0–PC31
PD8–PD31
PE0–PE31
SLCK
backup_nreset
rtc_alarm
32K RC
Oscillator
Slow Clock
Oscillator
SCKC_CR
12 MHz RC
Oscillator
int
SLCK
12 MHz
Main
Oscillator
MAINCK
PLLA PLLACK
UPLL UPLLCK
periph_nreset
periph_nreset
periph_clk[29..26]
dbgu_rxd
Shutdown
Controller
Power
Management
Controller
PIO
Controllers
periph_clk[2..59]
pck[0-2]
UHP48M
UHP12M
PCK
MCK
DDR sysclk
LCD Pixel clock
pmc_irq
Idle
periph_irq[29..26]
irq
fiq
dbgu_txd
Fuse Box
periph_clk[2..59]
periph_nreset
periph_irq[2..59]
In
Out
Enable
Embedded
Peripherals
Key
xxx Always Secured
xxx Programmable Secured
xxx Secured and Non-Secured
SAMA5D4 Series [DATASHEET]
37
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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