ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
Table 8-1.
Instance
ID
53
Peripheral Identifiers (Continued)
Instance
Name Instance Description
TRNG True Random Number Generator
External
Interrupt
–
54
GMAC0 Ethernet MAC 0
–
Wired-OR
Interrupt
–
–
55
GMAC1 Ethernet MAC 1
–
–
56
AIC
IRQ Interrupt ID
IRQ
–
57
SFC
Fuse Controller
–
–
58
–
Reserved
–
–
59
SECURAM Secured RAM
–
–
61
SMD
SMD Soft Modem
–
–
62
TWI3 Two-Wire Interface 3
–
–
63
–
Reserved
–
–
64
SFR
Special Function Register (1)
–
–
65
AIC
Advanced Interrupt Controller (1)
–
–
66
SAIC
Secured Advanced Interrupt
Controller (1)
–
–
67
L2CC
L2 Cache Controller (1)
–
–
Notes: 1. For security purposes, there is no matching clock but a peripheral ID only.
Clock Type
PCLOCK_LS
HCLOCK_LS +
PCLOCK_LS
HCLOCK_LS +
PCLOCK_LS
MCK2
PCLOCK_LS
–
PCLOCK_LS
SMDCK
PCLOCK_LS
–
–
–
Security
Type
PS
PS
PS
Non-
Secured
AS
–
AS
PS
PS
AS
Non-
Secured
In
Matrix
H32MX
H32MX
H32MX
H32MX
H32MX
–
H32MX
H32MX
H32MX
H32MX
H32MX
–
AS
H32MX
–
PS
H64MX
8.3 Peripheral Signal Multiplexing on I/O Lines
The SAMA5D4 product features five PIO controllers: PIOA, PIOB, PIOC, PIOD, and PIOE, that multiplex the I/O
lines of the peripheral set.
Each line can be assigned to one of three peripheral functions: A, B, or C. The multiplexing tables in the pin
description paragraphs define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO
Controllers.
Note that some peripheral functions which are output only, might be duplicated within the both tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is
mentioned, the PIO line resets in input with the pull-up enabled, so that the device is maintained in a static state as
soon as the reset is released. As a result, the bit corresponding to the PIO line in PIO_PSR (Peripheral Status
Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this function and the
corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address
lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also
enabled in this case.
SAMA5D4 Series [DATASHEET]
41
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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