ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
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MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
9. ARM Cortex-A5
9.1 Description
The ARM Cortex-A5 processor is a high-performance, low-power, ARM macrocell with an L1 cache subsystem
that provides full virtual memory capabilities. The Cortex-A5 processor implements the ARMv7 architecture and
runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java® byte codes in Jazelle® state.
The Cortex-A5 NEON Media Processing Engine (MPE) extends the Cortex-A5 functionality to provide support for
the ARM v7 Advanced SIMD v2 and Vector Floating-Point v4 (VFPv4) instruction sets. The Cortex-A5 NEON MPE
provides flexible and powerful acceleration for signal processing algorithms including multimedia such as image
processing, video decode/encode, 2D/3D graphics, and audio. Refer to the Cortex-A5 NEON Media Processing
Engine Technical Reference Manual.
The Cortex-A5 processor includes TrustZone technology to enhance security by partitioning the SoC’s hardware
and software resources in a Secure world for the security subsystem and a Normal world for the rest, enabling a
strong security perimeter to be built between the two. Refer to Security Extensions overview in the Cortex-A5
Technical Reference Manual. Refer to the ARM Architecture Reference Manual for details on how TrustZone
works in the architecture.
Note: All ARM publications referenced in this datasheet can be found at www.arm.com.
9.1.1
Power Management
The Cortex-A5 design supports the following main levels of power management:
Run Mode
Standby Mode
9.1.1.1 Run Mode
Run mode is the normal mode of operation where all of the processor functionality is available. Everything,
including core logic and embedded RAM arrays, is clocked and powered up.
9.1.1.2 Standby Mode
Standby mode disables most of the clocks of the processor, while keeping it powered up. This reduces the power
drawn to the static leakage current, plus a small clock power overhead required to enable the processor to wake
up from Standby mode. The transition from Standby mode to Run mode is caused by one of the following:
the arrival of an interrupt, either masked or unmasked
the arrival of an event, if standby mode was initiated by a Wait for Event (WFE) instruction
a debug request, when either debug is enabled or disabled
a reset.
9.2 Embedded Characteristics
In-order pipeline with dynamic branch prediction
ARM, Thumb, and ThumbEE instruction set support
TrustZone security extensions
Harvard level 1 memory system with a Memory Management Unit (MMU)
32 Kbytes Data Cache
32 Kbytes Instruction Cache
64-bit AXI master interface
ARM v7 debug architecture
Media Processing Engine (MPE) with NEON technology
Jazelle hardware acceleration
SAMA5D4 Series [DATASHEET]
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Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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