ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
Table 9-2. Cortex-A5 Modes and Registers Layout
User and
System
Monitor
Supervisor
R0
R0
R0
R1
R1
R1
R2
R2
R2
R3
R3
R3
R4
R4
R4
R5
R5
R5
R6
R6
R6
R7
R7
R7
R8
R8
R8
R9
R9
R9
R10
R10
R10
R11
R11
R11
R12
R12
R12
R13
R13_MON
R13_SVC
R14
R14_MON
R14_SVC
PC
PC
PC
Abort
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_ABT
R14_ABT
PC
Undefined
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_UND
R14_UND
PC
Interrupt
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_IRQ
R14_IRQ
PC
Fast Interrupt
R0
R1
R2
R3
R4
R5
R6
R7
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
PC
CPSR
CPSR
SPSR_MON
CPSR
SPSR_SVC
CPSR
SPSR_ABT
CPSR
SPSR_UND
CPSR
SPSR_IRQ
CPSR
SPSR_FIQ
Mode-specific banked registers
The core contains one CPSR, and six SPSRs for exception handlers to use. The program status registers:
hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operating mode
Figure 9-2.
Status Register Format
31 30 29 28 27
24 23
20 19
16 15
N
Z
C
V
Q
IT
[1:0]
J
Reserved
GE[3:0]
10 9 8 7 6 5 4
0
IT[7:2] E A I F T Mode
N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
Q: cumulative saturation flag
IT: If-Then execution state bits for the Thumb IT (If-Then) instruction
J: Jazelle bit, refer to the description of the T bit
GE: Greater than or Equal flags, for SIMD instructions
46 SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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