4. Initialize Secure Monitor software to handle exceptions that switch execution between the Secure and Non-
secure operating systems.
5. Optionally lock aspects of the secure state environment against further configuration.
6. Pass control through the Secure Monitor software to the non-secure OS with an SMC instruction.
7. Enable the Non-secure operating system to initialize. The required operations depend on the operating
system, and typically include initialization of caches, MMU, exception vectors, and stacks.
The overall security of the secure software depends on the system design, and on the secure software itself.
9.4.7 TrustZone
9.4.7.1 Hardware
TrustZone enables a single physical processor core to execute code safely and efficiently from both the Normal
world and the Secure world. This removes the need for a dedicated security processor core, saving silicon area
and power, and allowing high performance security software to run alongside the Normal world operating
environment.
The two virtual processors context switch via a new processor mode called monitor mode when changing the
currently running virtual processor.
Figure 9-3. TrustZone Hardware Implementation
9.4.7.2 Software
The mechanisms by which the physical processor can enter monitor mode from the Normal world are tightly
controlled, and are all viewed as exceptions to the monitor mode software. Software executing a dedicated
instruction can trigger entry to monitor, the Secure Monitor Call (SMC) instruction, or by a subset of the hardware
exception mechanisms. Configuration of the IRQ, FIQ, external Data Abort, and external Prefetch Abort
exceptions can cause the processor to switch into monitor mode.
The software that executes within monitor mode is implementation defined, but it generally saves the state of the
current world and restores the state of the world at the location to which it switches. It then performs a return-from-
exception to restart processing in the restored world.
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Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16