ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
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MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
TLB maintenance and configuration operations are controlled through a dedicated coprocessor, CP15, integrated
with the core. This coprocessor provides a standard mechanism for configuring the L1 memory system.
Refer to the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for a full architectural
description of the ARMv7 VMSA.
9.5.2
Memory Management System
The Cortex-A5 processor supports the ARM v7 VMSA including the TrustZone security extension. The translation
of a Virtual Address (VA) used by the instruction set architecture to a Physical Address (PA) used in the memory
system and the management of the associated attributes and permissions is carried out using a two-level MMU.
The first level MMU uses a Harvard design with separate micro TLB structures in the PFU for instruction fetches
(IuTLB) and in the DPU for data read and write requests (DuTLB).
A miss in the micro TLB results in a request to the main unified TLB shared between the data and instruction sides
of the memory system. The TLB consists of a 128-entry two-way set-associative RAM based structure. The TLB
page-walk mechanism supports page descriptors held in the L1 data cache. The caching of page descriptors is
configured globally for each translation table base register, TTBRx, in the system coprocessor, CP15.
The TLB contains a hitmap cache of the page types which have already been stored in the TLB.
9.5.2.1 Memory types
Although various different memory types can be specified in the page tables, the Cortex-A5 processor does not
implement all possible combinations:
Write-through caches are not supported. Any memory marked as write-through is treated as Non-cacheable.
The outer shareable attribute is not supported. Anything marked as outer shareable is treated in the same
way as inner shareable.
Write-back no write-allocate is not supported. It is treated as write-back write-allocate.
Table 9-5 shows the treatment of each different memory type in the Cortex-A5 processor in addition to the
architectural requirements.
SAMA5D4 Series [DATASHEET]
53
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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