ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
If the TLB finds a matching entry, it uses the information in the entry as follows:
1. The access permission bits and the domain determine if the access is enabled. If the matching entry does
not pass the permission checks, the MMU signals a memory abort. Refer to the ARM Architecture Reference
Manual, ARMv7-A and ARMv7-R edition for a description of access permission bits, abort types and
priorities, and for a description of the Instruction Fault Status Register (IFSR) and Data Fault Status Register
(DFSR).
2. The memory region attributes specified in both the TLB entry and the CP15 c10 remap registers determine if
the access is
̶ Secure or Non-secure
̶ Shared or not
̶ Normal memory, Device, or Strongly-ordered
For more information refer to the Cortex-A5 Technical Reference Manual, Memory region remap.
3. The TLB translates the virtual address to a physical address for the memory access.
9.5.5
Interaction with Memory System
The MMU can be enabled or disabled as described in the ARM Architecture Reference Manual, ARMv7-A and
ARMv7-R edition.
9.5.6
External Aborts
External memory errors are defined as those that occur in the memory system rather than those that are detected
by the MMU. External memory errors are expected to be extremely rare. External aborts are caused by errors
flagged by the AXI interfaces when the request goes external to the Cortex-A5 processor. External aborts can be
configured to trap to Monitor mode by setting the EA bit in the Secure Configuration Register. For more information
refer to the Cortex-A5 Technical Reference Manual.
9.5.6.1 External Aborts on Data Write
Externally generated errors during a data write can be asynchronous. This means that the r14_abt on entry into
the abort handler on such an abort might not hold the address of the instruction that caused the exception.
The DFAR is Unpredictable when an asynchronous abort occurs.
Externally generated errors during data read are always synchronous. The address captured in the DFAR matches
the address which generated the external abort.
9.5.6.2 Synchronous and Asynchronous Aborts
Chapter 4, System Control in the Cortex-A5 Technical Reference Manual describes synchronous and
asynchronous aborts, their priorities, and the IFSR and DFSR. To determine a fault type, read the DFSR for a data
abort or the IFSR for an instruction abort.
The processor supports an Auxiliary Fault Status Register for software compatibility reasons only. The processor
does not modify this register because of any generated abort.
9.5.7
MMU Software Accessible Registers
The system control coprocessor registers, CP15, in conjunction with page table descriptors stored in memory,
control the MMU.
Access all the registers with instructions of the form:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
MCR p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
CRn is the system control coprocessor register. Unless specified otherwise, CRm and Opcode_2 Should Be Zero.
56 SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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