ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
9.5.3.2 Main TLB
Misses from the instruction and data micro TLBs are handled by a unified main TLB. Accesses to the main TLB
take a variable number of cycles, according to competing requests from each of the micro TLBs and other
implementation-dependent factors.
The main TLB is 128-entry two-way set-associative.
TLB match process
Each TLB entry contains a virtual address, a page size, a physical address, and a set of memory properties. Each
is marked as being associated with a particular application space (ASID), or as global for all application spaces.
The CONTEXTIDR determines the currently selected application space.
A TLB entry matches when these conditions are true:
Its virtual address matches that of the requested address.
Its Non-secure TLB ID (NSTID) matches the Secure or Non-secure state of the MMU request.
Its ASID matches the current ASID in the CONTEXTIDR or is global.
The operating system must ensure that, at most, one TLB entry matches at any time. The TLB can store entries
based on the following block sizes:
Supersections
Sections
Large pages
Small pages
Describe 16 Mbyte blocks of memory
Describe 1 Mbyte blocks of memory
Describe 64 Kbyte blocks of memory
Describe 4 Kbyte blocks of memory
Supersections, sections and large pages are supported to permit mapping of a large region of memory while using
only a single entry in the TLB. If no mapping for an address is found within the TLB, then the translation table is
automatically read by hardware and a mapping is placed in the TLB.
9.5.4
Memory Access Sequence
When the processor generates a memory access, the MMU:
1. Performs a lookup for the requested virtual address and current ASID and security state in the relevant
instruction or data micro TLB.
2. If there is a miss in the micro TLB, performs a lookup for the requested virtual address and current ASID and
security state in the main TLB.
3. If there is a miss in main TLB, performs a hardware translation table walk.
The MMU can be configured to perform hardware translation table walks in cacheable regions by setting the IRGN
bits in Translation Table Base Register 0 and Translation Table Base Register 1. If the encoding of the IRGN bits
is write-back, an L1 data cache lookup is performed and data is read from the data cache. If the encoding of the
IRGN bits is write-through or non-cacheable, an access to external memory is performed. For more information
refer to the Cortex-A5 Technical Reference Manual.
The MMU might not find a global mapping, or a mapping for the currently selected ASID, with a matching Non-
secure TLB ID (NSTID) for the virtual address in the TLB. In this case, the hardware does a translation table walk
if the translation table walk is enabled by the PD0 or PD1 bit in the Translation Table Base Control Register. If
translation table walks are disabled, the processor returns a Section Translation fault. For more information refer to
the Cortex-A5 Technical Reference Manual.
SAMA5D4 Series [DATASHEET]
55
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
Share Link: 
