Figure 10-3. Application Test Environment Example
Test Adaptor
JTAG
Interface
Tester
ICE/JTAG Chip n
Chip 2
SAM device
Chip 1
SAM-based Application Board In Test
10.5 Debug and Test Pin Description
Table 10-1.
Pin Name
NRST
TST
NTRST
TCK
TDI
TDO
TMS
JTAGSEL
SWCLK
SWDIO
DRXD
DTXD
Debug and Test Pin List
Function
Reset/Test
Microprocessor Reset
Test Mode Select
ICE and JTAG
Test Reset Signal
Test Clock
Test Data In
Test Data Out
Test Mode Select
JTAG Selection
SWD
Serial Debug Clock
Serial Debug IO
Debug Unit
Debug Receive Data
Debug Transmit Data
Type
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input/Output
Input
Output
Active Level
Low
High
Low
–
–
–
–
–
–
–
–
–
60 SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16