ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
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MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
Table 9-5. Treatment of Memory Attributes
Memory Type Attribute Shareability Other Attributes
Strongly Ordered
—
—
Device
Non-shareable —
Shareable —
Non-cacheable
Write-through cacheable
Non-shareable Write-back cacheable,
write allocate
Write-back cacheable,
no write allocate
Non-cacheable
Normal
Inner
shareable
Write-through cacheable
Write-back cacheable,
write allocate
Write-back cacheable,
no write allocate
Non-cacheable
Outer
shareable
Write-through cacheable
Write-back cacheable,
write allocate
Write-back cacheable,
no write allocate
Notes
—
—
—
Does not access L1 caches
Treated as non-cacheable
Can dynamically switch to no write allocate, if more than
three full cache lines are written in succession
Treated as non-shareable write-back cacheable, write
allocate
—
Treated as inner shareable non-cacheable
Treated as inner shareable non-cacheable unless the SMP
bit in the Auxiliary Control Register is set (ACTLR[6] = b1).
If this bit is set the area is treated as write-back cacheable
write allocate.
Treated as inner shareable non-cacheable
Treated as inner shareable non-cacheable unless the SMP
bit in the Auxiliary Control Register is set (ACTLR[6] = b1).
If this bit is set the area is treated as write-back cacheable
write allocate.
9.5.3
TLB Organization
TLB Organization is described in the sections that follow:
Micro TLB
Main TLB
9.5.3.1 Micro TLB
The first level of caching for the page table information is a micro TLB of 10 entries that is implemented on each of
the instruction and data sides. These blocks provide a lookup of the virtual addresses in a single cycle.
The micro TLB returns the physical address to the cache for the address comparison, and also checks the access
permissions to signal either a Prefetch Abort or a Data Abort.
All main TLB related maintenance operations affect both the instruction and data micro TLBs, causing them to be
flushed. In the same way, any change of the following registers causes the micro TLBs to be flushed:
Context ID Register (CONTEXTIDR)
Domain Access Control Register (DACR)
Primary Region Remap Register (PRRR)
Normal Memory Remap Register (NMRR)
Translation Table Base Registers (TTBR0 and TTBR1)
54 SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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