ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
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'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
9.4.2
Processor Operating States
The processor has the following instruction set states controlled by the T bit and J bit in the CPSR.
ARM state:
The processor executes 32-bit, word-aligned ARM instructions.
Thumb state:
The processor executes 16-bit and 32-bit, halfword-aligned Thumb instructions.
ThumbEE state:
The processor executes a variant of the Thumb instruction set designed as a target for dynamically
generated code. This is code compiled on the device either shortly before or during execution from a
portable bytecode or other intermediate or native representation.
Jazelle state:
The processor executes variable length, byte-aligned Java bytecodes.
The J bit and the T bit determine the instruction set used by the processor. Table 9-1 shows the encoding of these
bits.
Table 9-1.
J
0
0
1
1
CPSR J and T Bit Encoding
T
Instruction Set State
0
ARM
1
Thumb
0
Jazelle
1
ThumbEE
Changing between ARM and Thumb states does not affect the processor mode or the register contents. Refer to
the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for information on entering and exiting
ThumbEE state.
9.4.2.1 Switching State
It is possible to change the instruction set state of the processor between:
ARM state and Thumb state using the BX and BLX instructions.
Thumb state and ThumbEE state using the ENTERX and LEAVEX instructions.
ARM and Jazelle state using the BXJ instruction.
Thumb and Jazelle state using the BXJ instruction.
Refer to the ARM Architecture Reference Manual for more information about changing instruction set state.
9.4.3
Cortex-A5 Registers
This view provides 16 ARM core registers, R0 to R15, that include the Stack Pointer (SP), Link Register (LR), and
Program Counter (PC). These registers are selected from a total set of either 31 or 33 registers, depending on
whether or not the Security Extensions are implemented. The current execution mode determines the selected set
of registers, as shown in Table 9-2. This shows that the arrangement of the registers provides duplicate copies of
some registers, with the current register selected by the execution mode. This arrangement is described as
banking of the registers, and the duplicated copies of registers are referred to as banked registers.
SAMA5D4 Series [DATASHEET]
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Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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