ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
E: Endianness execution state bit. Controls the load and store endianness for data accesses. This bit is
ignored by instruction fetches.
̶ E = 0: Little endian operation
̶ E = 1: Big endian operation
A: Asynchronous abort disable bit. Used to mask asynchronous aborts.
I: Interrupt disable bit. Used to mask IRQ interrupts.
F: Fast interrupt disable bit. Used to mask FIQ interrupts.
T: Thumb execution state bit. This bit and the J execution state bit, bit [24], determine the instruction set state
of the processor, ARM, Thumb, Jazelle, or ThumbEE.
Mode: five bits to encode the current processor mode. The effect of setting M[4:0] to a reserved value is
UNPREDICTABLE.
Table 9-3.
Processor Mode vs. Mode Field
Mode
USR
FIQ
IRQ
SVC
MON
ABT
UND
SYS
Reserved
M[4:0]
10000
10001
10010
10011
10110
10111
11011
11111
Other
9.4.3.1 CP15 Coprocessor
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list
below:
Cortex A5
Caches (ICache, DCache and write buffer)
MMU
Security
Other system options
To control these features, CP15 provides 16 additional registers. Refer to Table 9-4.
Table 9-4. CP15 Registers
Register
Name
0
ID Code(1)
0
Cache type(1)
1
Control(1)
1
Security(1)
2
Translation Table Base
3
Domain Access Control
4
Reserved
Read/Write
Read/Unpredictable
Read/Unpredictable
Read/Write
Read/Write
Read/Write
Read/Write
None
SAMA5D4 Series [DATASHEET]
47
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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