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ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation

Part Name
Description
MFG CO.
ATSAMA5D41A-CU
Atmel
Atmel Corporation Atmel
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
8. Peripherals
8.1 Peripheral Mapping
As shown in Figure 5-1 “Memory Mapping”, the peripherals are mapped in the upper 256 Mbytes of the address
space between the addresses 0xF000 0000 and 0xFFFF FFFF.
Each user peripheral is allocated 16 Kbytes of the address space.
8.2 Peripheral Identifiers
In the following table, AS stands for “Always Secured” and PS stands for “Programmable Secured”.
Table 8-1.
Instance
ID
0
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
22
23
24
Peripheral Identifiers
Instance
Name Instance Description
SAIC FIQ Interrupt ID
SYS
System Controller
ARM
PIT
WDT
PIOD
USART0
USART1
Performance Monitor Unit (PMU)
Periodic Interval Timer
Watchdog Timer
Parallel I/O Controller D
Universal Synchronous
Asynchronous Receiver
Transceiver 0
Universal Synchronous
Asynchronous Receiver
Transceiver 1
XDMAC0 DMA Controller 0
ICM
CPKCC
AES
AESB
TDES
SHA
MPDDRC
MATRIX1
MATRIX0
VDEC
SBM
HSMC
PIOA
PIOB
Integrity Check Monitor
Classic Public Key Crypto
Controller
Advanced Encryption Standard
AES Bridge
Triple Data Encryption Standard
SHA Signature
MPDDR Controller
H32MXMX, 32-bit AHB Matrix
H64MX, 64-bit AHB Matrix
Video Decoder
Secure Box Module
Multi-bit ECC Interrupt
Parallel I/O Controller A
Parallel I/O Controller B
External
Interrupt
FIQ
Wired-OR
Interrupt
PMC, RSTC,
RTC, SHDWC
Clock Type
MCK2
MCK2
PCK
MCK2
MCK2
PCLOCK_LS
PCLOCK_LS
PCLOCK_LS
HCLOCK_HS +
PCLOCK_HS
PCLOCK_LS
PCLOCK_HS
PCLOCK_LS
PCLOCK_HS
PCLOCK_LS
PCLOCK_LS
HCLOCK_HS
PCLOCK_LS
PCLOCK_HS
PCLOCK_HS
MCK2
PCLOCK_LS
PCLOCK_LS
PCLOCK_LS
Security
Type
AS
AS
AS
AS
AS
AS
AS
AS
AS
AS
AS
AS
AS
AS
AS
AS
AS
AS
PS
AS
PS
PS
PS
In
Matrix
H32MX
H32MX
H64MX
H32MX
H32MX
H32MX
H32MX
H32MX
H64MX
H32MX
H64MX
H32MX
H64MX
H32MX
H32MX
H64MX
H32MX
H64MX
H64MX
H32MX
H32MX
H32MX
H32MX
SAMA5D4 Series [DATASHEET]
39
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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