ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
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Description
MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
Table 13-1. L2CC Master Port Behavior
Bit 30
DLEN
Bit 27
Bit 23
DLFWRDIS IDLEN
Original Read
Address from L1
Read
AXI Burst
Address to L3 AXI Burst Type Length
Targeted Cache
Lines
0
0 or 1
0 or 1
0x00
0x00
WRAP
0x3, 4x64-bit 0x00
0
0 or 1
0 or 1
0x20
0x20
WRAP
0x3, 4x64-bit 0x20
1
0 or 1
0
0x00
0x00
WRAP
0x7, 8x64-bit 0x00 and 0x20
1
1
0
0x08 or 0x10 or 0x18 0x08
WRAP
0x3, 4x64-bit 0x00
1
0
0
0x08 or 0x10 or 0x18 0x00
WRAP
0x7, 8x64-bit 0x00 and 0x20
1
0 or 1
0
0x20
0x20
WRAP
0x7, 8x64-bit 0x00 and 0x20
1
1
0
0x28 or 0x30 or 0x38 0x28
WRAP
0x3, 4x64-bit 0x20
1
0
0
0x28 or 0x30 or 0x38 0x20
WRAP
0x7, 8x64-bit 0x00 and 0x20
1
0 or 1
1
0x00
0x00
INCR or WRAP 0x7, 8x64-bit 0x00 and 0x20
1
1
1
0x08 or 0x10 or 0x18 0x08
WRAP
0x3, 4x64-bit 0x00
1
0
1
0x08 or 0x10 or 0x18 0x00
INCR or WRAP 0x7, 8x64-bit 0x00 and 0x20
1
0 or 1
1
0x20
0x20
INCR
0x7, 8x64-bit 0x20 and 0x40
1
1
1
0x28 or 0x30 or 0x38 0x28
WRAP
0x3, 4x64-bit 0x20
1
Notes:
0
1
0x28 or 0x30 or 0x38 0x20
INCR
0x7, 8x64-bit 0x20 and 0x40
1. Double linefills are not issued for prefetch reads if you enable exclusive cache configuration.
2. Double linefills are not launched when crossing a 4-Kbyte boundary.
3. Double linefills only occur if a WRAP4 or an INCR4 64-bit transaction is received on the slave ports. This transaction is most
commonly seen as a result of a cache linefill in a master, but can be produced by a master when accessing memory marked
as inner non-cacheable.
SAMA5D4 Series [DATASHEET]
87
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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