Electrical Specifications
• Parameters not present for VCC:
— No socket loadline slope - SKT_LL
— No socket loadline tolerance band
— No maximum overshoot above VID (OS_AMP)
— No maximum overshoot time duration above VID (OS_TIME)
— No peak-to-peak ripple amplitude (RIPPLE)
— No thermal compensation voltage drift (THERMAL_DRIFT)
— No maximum DC test (current I_DC_MAX)
— No minimum DC test (current I_DC_MIN)
• Parameters present for VCC:
— Tolerance band (TOB) of ±50 mV
Table 4-28.Processor Core Active and Idle Mode DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit Note
VID
VCC
VCC,BOOT
ICC
IAH
dICC/DT
VID Range
VCC for processor core
Default VCC voltage for initial
power up
ICC for processor core
Dual Core
Single Core
ICC Auto-Halt
Dual Core
Single Core
VCC power supply current slew rate
at the processor pin package
Dual Core
Single Core
0.8
1.175
See Table 4-26 and Figure 4-2
0.800 - 1.175
1.045
1.1
1.26
10.8
5.4
6.5
3.25
5
2.5
V
V
2, 3
V
A
A
A/µs
NOTES:
1.
Unless otherwise noted, all specifications in this table are based on estimates and
simulations or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
2.
Each processor is programmed with voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual VID values are calibrated during
manufacturing such that two processors at the same frequency may have different
settings within the VID range. Please note this differs from the VID employed by the
processor during a power management event.
3.
These are pre-silicon estimates and are subject to change.
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Datasheet