Electrical Specifications
Table 4-31.DDR2 Signal Group DC Specifications (Sheet 2 of 2)
Symbol
VOL
VOH
RON
ILI
VREF
CI/O
Parameter
Output Low Voltage
DDR2
DDR3
Output High Voltage
DDR2
DDR3
DDR2 Clock Buffer On
Resistance
Input Leakage Current
DDR Reference Voltage
DQ/DQS/DQSB DDR2 I/O
Pin Capacitance
Min
1.47
1.22
VCCSM / 2
3.5
Typ
22
VCCSM / 2
3.5
Max
0.27
0.20
10
VCCSM / 2
3.6
Units
V
Ī©
μA
pF
Notes1,9
9
4,9
5
8
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as
a logical low value.
3.
VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as
a logical high value.
4.
VIH and VOH may experience excursions above VCCSM. However, input signal drivers must
comply with the signal quality specifications.
5.
This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V
characteristics.
6.
The minimum and maximum values for these signals are programmable by BIOS
7.
DDR2 values are pre-silicon estimations and subject to change.
8.
VCCSM varies with typical/min/max cases. Refer Table 4-29 for details.
9.
Determined with 2x Buffer Strength Settings into a 50 to 0.5x VCCSM test load.
10. DDR_VREF could either be from external or internal reference voltage.
4.10.3.3 LGIO Signal DC Specification
Table 4-32.GTL Signal Group DC Specifications
Symbol
Parameter
Min
VCCP
GTLREF
RODT
VIH
I/O Voltage
GTL Reference Voltage
On Die Termination
Input High Voltage
VIL
VOH
RTT
RON
ILI
CPAD
Input Low Voltage
Output High Voltage
Termination Resistance
Buffer on Resistance
Input Leakage Current
Pad Capacitance
1
2/3 VCCP
55
GTLREF +
0.1
-0.1
VCCP - 0.1
20
14
-100
2.35
NOTES:See notes in the next page
Typ
1.05
55
25
2.5
Max
1.1
2/3 VCCP
55
VCCP + 0.1
Units
V
V
Ohm
V
Notes1
6
10
3,6
GTLREF - 0.1
V
2,4
VCCP
V
6
70
Ohm
7
40
Ī©
5
100
μA
8
2.6
pF
9
Datasheet
47