AU80610006225AASLBXC View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'AU80610006225AASLBXC' PDF : 80 Pages View PDF
Electrical Specifications
4.10.3.4 DDR3_DRAM_PWROK DC Specification
4.10.3.5
Symbol
Parameter
VIL
Input Low Voltage
VIH
Input High Voltage
LI
Input leakage
Min
-
1.25
-
Max
0.29
-
20
Units Notes1
V
V
2
uA
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
These are pre-silicon estimates and are subject to change.
2.
VIH may experience excursions above VCCSM.. However, input signal drivers must comply
with the signal quality specifications.
JTAG DC Specification
Table 4-37.TAP Signal Group DC Specification
Symbol
Parameter
Min
RPDGTL
VT-
VT+
ILI
GTL mode pull-down
impedance (JTAG mode)
Input fall transition
threshold voltage
Input rise transition
threshold voltage
Input Leakage Current
0.54* VCCP
0.74* VCCP
Typ
25
-
-
Max
Units Notes1
Ohm
0.66* VCCP
V
2,4
0.86* VCCP
V
1,3
50
uA
NOTES:
1.
Positive transitions must cross above VT+(max) to trigger input.
2.
Negative transitions must cross below VT-(min) to trigger input.
3.
Input low noise must not cross VT+(min).
4.
Input high noise must not cross VT-(max).
5.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
4.10.3.6
Display DC Specification
The Analog Video Signal DC Specifications are referred to the VESA Video Signal
Standard, version 1 revision 2.
Table 4-38.CRT_DDC_DATA. CRT_DDC_CLK, LDDC_DATA, LDDC_CLK, LCTLA_CLK, and
LCTLB_DATA DC Specification (Sheet 1 of 2)
Symbol
Parameter
Standard mode
100kbits/s
Min
Max
Units Notes1
VIL
Input Low Voltage
VIH
Input High Voltage
-0.5
0.3 VCCGIO
V
0.7 VCCGIO 0.5 + VCCGIO
V
50
Datasheet
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