C8051F067 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F067' PDF : 328 Pages View PDF
C8051F060/1/2/3/4/5/6/7
1.8. 16-Bit Analog to Digital Converters
The C8051F060/1/2/3/4/5/6/7 devices have two on-chip 16-bit SAR ADCs (ADC0 and ADC1), which can
be used independently in single-ended mode, or together in differential mode. ADC0 and ADC1 can
directly access on-chip or external RAM, using the DMA interface. With a maximum throughput of 1 Msps,
the ADCs offer 16 bit performance with two available linearity grades. ADC0 and ADC1 each have the
capability to use dedicated, on-chip voltage reference circuitry or an external voltage reference source.
The ADCs are under full control of the CIP-51 microcontroller via the associated Special Function Regis-
ters. The system controller can also put the ADCs into shutdown mode to save power.
Conversions can be started in four ways; a software command, an overflow of Timer 2, an overflow of
Timer 3, or an external signal input. This flexibility allows the start of conversion to be triggered by software
events, external HW signals, or a periodic timer overflow signal. The two ADCs can operate independently,
or be synchronized to perform conversions at the same time. Conversion completions are indicated by sta-
tus bits, and can generate interrupts. The resulting 16-bit data words are latched into SFRs upon comple-
tion of a conversion. A DMA interface is also provided, which can gather conversions from the ADCs, and
directly store them to on-chip or external RAM.
ADC0 also contains Window Compare registers, which can be configured to interrupt the controller when
ADC0 data is within or outside of a specified range. ADC0 can monitor a key voltage continuously in back-
ground mode, and not interrupt the controller unless the converted data is within the specified window.
AIN0
AIN0G
(DC, -0.2 to 0.6 V)
Start Conversion
16-Bit
SAR
16
ADC0
Write to AD0BUSY
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
ADC0
Window
Compare
Logic
Configuration and Control ADC Data
Registers
Registers
DMA
Interface
AIN1
AIN1G
(DC, -0.2 to 0.6 V)
16-Bit
SAR
16
ADC1
Start Conversion
Write to AD1BUSY
Timer 3 Overflow
CNVSTR1
Timer 2 Overflow
Write to AD0BUSY
Figure 1.12. 16-Bit ADC Block Diagram
Rev. 1.2
33
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