C8051F067 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F067' PDF : 328 Pages View PDF
C8051F060/1/2/3/4/5/6/7
4. Pinout and Package Definitions
Table 4.1. Pin Definitions
Name
VDD
DGND
AV+
AVDD
AGND
TMS
TCK
TDI
TDO
/RST
XTAL1
XTAL2
MONEN
VREF
VREF0
Pin Numbers
F060 F061 F064 F065 Type Description
F062 F063 F066 F067
37, 64, 26, 40, 37, 64, 26, 40,
90 55 90 55
Digital Supply Voltage. Must be tied to +2.7 to
+3.6 V.
38, 63, 27, 39, 38, 63, 27, 39,
89 54 89 54
Digital Ground. Must be tied to Ground.
11, 16, 7, 10, 11, 16, 7, 10,
24 18 24 18
Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
13 23 13 23
Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
10, 14, 6, 11, 10, 14, 6, 11,
17, 23 19, 22 17, 23 19, 22
Analog Ground. Must be tied to Ground.
96 52 96 52 D In JTAG Test Mode Select with internal pull-up.
97 53 97 53 D In JTAG Test Clock with internal pull-up.
98 56 98 56 D In JTAG Test Data Input with internal pull-up. TDI is
latched on the rising edge of TCK.
99 57 99 57 D Out JTAG Test Data Output with internal pull-up. Data is
shifted out on TDO on the falling edge of TCK. TDO
output is a tri-state driver.
100 58 100 58 D I/O Device Reset. Open-drain output of internal VDD
monitor. Is driven low when VDD is <2.7 V and
MONEN is high. An external source can initiate a
system reset by driving this pin low.
26 20 26 20 A In Crystal Input. This pin is the return for the internal
oscillator circuit for a crystal or ceramic resonator.
For a precision internal clock, connect a crystal or
ceramic resonator from XTAL1 to XTAL2. If over-
driven by an external CMOS clock, this becomes
the system clock.
27 21 27 21 A Out Crystal Output. This pin is the excitation driver for a
crystal or ceramic resonator.
28 63 28 63 D In VDD Monitor Enable. When tied high, this pin
enables the internal VDD monitor, which forces a
system reset when VDD is < 2.7 V. When tied low,
the internal VDD monitor is disabled. Recom-
mended configuration is to connect directly to VDD.
4
61
4
61 A Out Bandgap Voltage Reference Output
21 15 21 15 A I/O Bandgap Voltage Reference Output for ADC0.
ADC0 Voltage Reference Input.
Rev. 1.2
39
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