C8051F060/1/2/3/4/5/6/7
Table 4.1. Pin Definitions (Continued)
Name
VRGND0
VBGAP0
VREF1
VRGND1
VBGAP1
VREF2
VREFD
AIN0
AIN0G
AIN1
AIN1G
CNVSTR0
CNVSTR1
CANTX
CANRX
DAC0
DAC1
P0.0
P0.1
P0.2
P0.3
P0.4
Pin Numbers
F060 F061 F064 F065
F062 F063 F066 F067
20 14 20 14
22 16 22 16
6
2
6
2
7
3
7
3
5
1
5
1
2
62
3
18 12 18 12
19 13 19 13
9
5
9
5
8
4
8
4
15
9
15
9
12
8
12
8
94 59
95 60
25 17
1
64
62 51 62 51
61 50 61 50
60 49 60 49
59 48 59 48
58 47 58 47
Type Description
A In ADC0 Voltage Reference Ground. This pin should
be grounded if using the ADC.
A Out ADC0 Bandgap Bypass Pin.
A I/O Bandgap Voltage Reference Output for ADC1.
ADC1 Voltage Reference Input.
A In ADC1 Voltage Reference Ground. This pin should
be grounded if using the ADC.
A Out ADC1 Bandgap Bypass Pin.
A In ADC2 Voltage Reference Input.
A In ADC2, DAC0, and DAC1 Voltage Reference Input.
A In DAC0 and DAC1 Voltage Reference Input.
A In ADC0 Signal Input (See ADC0 Specification for
complete description).
A In ADC0 DC Bias Input (See ADC0 Specification for
complete description).
A In ADC1 Signal Input (See ADC1 Specification for
complete description).
A In ADC1 DC Bias Input (See ADC1 Specification for
complete description).
D In External Conversion Start Source for ADC0
D In External Conversion Start Source for ADC1
D Out Controller Area Network Transmit Output.
D In Controller Area Network Receive Input.
A Out Digital to Analog Converter 0 Voltage Output. (See
DAC Specification for complete description).
A Out Digital to Analog Converter 1 Voltage Output. (See
DAC Specification for complete description).
D I/O Port 0.0. See Port Input/Output section for complete
description.
D I/O Port 0.1. See Port Input/Output section for complete
description.
D I/O Port 0.2. See Port Input/Output section for complete
description.
D I/O Port 0.3. See Port Input/Output section for complete
description.
D I/O Port 0.4. See Port Input/Output section for complete
description.
40
Rev. 1.2