C8051F060/1/2/3/4/5/6/7
1.11. Analog Comparators
The C8051F060/1/2/3/4/5/6/7 MCUs include three analog comparators on-chip. The comparators have
software programmable hysteresis and response time. Each comparator can generate an interrupt on its
rising edge, falling edge, or both. The interrupts are capable of waking up the MCU from sleep mode, and
Comparator 0 can be used as a reset source. The output state of the comparators can be polled in soft-
ware or routed to Port I/O pins via the Crossbar. Outputs from the comparator can be routed through the
crossbar. The comparators can be programmed to a low power shutdown mode when not in use.
(Port I/O)
CPn Output
CROSSBAR
3 Comparators
CPn+
CPn-
+
CPn
-
Comparator inputs
Port 2.[7:2]
SFR's
(Data
and
Control)
Figure 1.15. Comparator Block Diagram
CIP-51
and
Interrupt
Handler
36
Rev. 1.2