CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
10.1.4 Gen Map 0–6 End Address High (I/O)
Register Name: Gen Map 0–6 End Address High (I/O)
I/O Index: 0Bh, 0Fh, 13h, 1Bh, 23h, 2Bh, 33h
Memory Offset: 80Bh, 80Fh, 813h, 81Bh, 823h, 82Bh, 833h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Register Per: socket
Register Compatibility Type: 365
Bit 2
Bit 1
Bit 0
End Address 15:8 (I/O)
R/W:00000000
There are seven separate Gen Map End Address High registers, each with identical fields. These
registers are located at the following indexes:
Index
0Bh
0Fh
13h
1Bh
23h
2Bh
33h
Memory Offset
80Bh
80Fh
813h
81Bh
823h
82Bh
833h
Gen Map End Address High
Gen Map 5 End Address High
Gen Map 6 End Address High
Gen Map 0 End Address High
Gen Map 1 End Address High
Gen Map 2 End Address High
Gen Map 3 End Address High
Gen Map 4 End Address High
Default Operation
I/O Window 0
I/O Window 1
Memory Window 0
Memory Window 1
Memory Window 2
Memory Window 3
Memory Window 4
Bits 7:0 — End Address 15:8 (I/O)
This register contains the most-significant byte of the address of the I/O space End Address.
122
GENERAL WINDOW MAPPING REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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