CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
10.2.6 Gen Map 0–6 Offset Address High (Memory)
Register Name: Gen Map 0–6 Offset Address High (Memory)
I/O Index: 15h, 1Dh, 25h, 2Dh, 35h, 37h, 39h
Memory Offset: 815h, 81Dh, 825h, 82Dh, 835h, 837h, 839h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Register Per: socket
Register Compatibility Type: 365
Bit 2
Bit 1
Bit 0
Write Protect REG Setting
Offset Address 25:20 (Memory)
R/W:0
R/W:0
R/W:000000
There are seven separate Gen Map Offset Address High registers, each with identical fields. These
registers are located at the following indexes:
I/O Index
15h
1Dh
25h
2Dh
35h
37h
39h
Memory Offset
815h
81Dh
825h
82Dh
835h
837h
839h
Gen Map Offset Address High
Gen Map 0 Offset Address High
Gen Map 1 Offset Address High
Gen Map 2 Offset Address High
Gen Map 3 Offset Address High
Gen Map 4 Offset Address High
Gen Map 5 Offset Address High
Gen Map 6 Offset Address High
Default Operation
Memory Window 0
Memory Window 1
Memory Window 2
Memory Window 3
Memory Window 4
I/O Window 0
I/O Window 1
Bits 5:0 — Offset Address 25:20 (Memory)
This field contains the most-significant six bits of the Memory Offset Address.
Bit 6 — REG Setting
0
REG# (see page 15) is not active for accesses made through this window.
1
REG# is active for accesses made through this window.
This bit determines whether REG# (see page 15) is active for accesses made through this
window. CIS (card information structure) memory is accessed by setting this bit to ‘1’.
Bit 7 — Write Protect
0
Writes to the card through this window are allowed.
1
Writes to the card through this window are not allowed.
This bit determines whether writes to the card through this window are allowed.
See the description of the Offset Address field associated with bits 7:0 of the Gen Map 5–6 Offset
Address Low register (on page 123).
130
GENERAL WINDOW MAPPING REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
Share Link: 
