CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
3.3 Host Access to Registers
The CL-PD6833 CardBus registers can be accessed in Memory-Mapped mode only. Other CL-PD6833 reg-
isters can be accessed either in Memory-Mapped mode or I/O-Mapped mode. To access registers in Mem-
ory-Mapped mode, program the CL-PD6833 memory base address offset 10h in the configuration space.
To access registers in I/O-Mapped mode, program offset 44h in the configuration space accordingly. In I/O-
Mapped mode, the CL-PD6833 registers are accessed through an 8-bit indexing mechanism. An Index reg-
ister scheme allows a large number of internal registers to be accessed by the CPU using only two I/O
addresses.
The Index register (see Chapter 7, “OPERATION REGISTERS”) is used to specify which of the internal reg-
isters the CPU accesses next. The value in the Index register is called the Register Index and is the number
that specifies a unique internal register. The Data register is used by the CPU to read and write the internal
register specified by the Index register.
INTERNAL REGISTERS
7FH
7EH REGISTER
•
INDEXES
•
•
02H
01H
00H
LOW MID. BYTE
LOW BYTE
X
X
DATA
INDEX
I/O
BASE ADDRESS + 1
I/O
BASE ADDRESS
I/O ADDRESSES
Figure 3-14. Indexed 8-Bit Register Structure
The following code segment demonstrates
use of an indexed 8-bit register:
mov dx, I/O_Base_Address
mov al, 02h
mov ah, 3Ch
out dx, ax
X
X
INTERNAL REGISTERS
REGISTER
INDEXES
3CH
02H
3CH
I/O
BASE ADDRESS + 1
02H
I/O
BASE ADDRESS
I/O ADDRESSES
Figure 3-15. Indexed 8-Bit Register Example
42
INTRODUCTION TO THE CL-PD6833
ADVANCE DATA BOOK v0.3
June 1998
Share Link: 
