CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5. PCI CONFIGURATION REGISTERS
The CL-PD6833 has two PCI Configuration register sets. Each of these register sets corresponds to a
socket. The second socket is the second function and starts at 100h. These register sets occupy config-
uration offsets 00h–4Fh. The register sets vary only in the function number (see PCI Bus Specification,
Rev. 2.1 for further information). They control basic PCI bus functionality. PCMCIA Operation registers
are accessed through either the Memory Base Address register or the I/O Base Address register. The
registers in this section are specific to each socket.
Table 5-1. PCI Configuration Registers Quick Reference
Register Name
Vendor ID and Device ID
(Device ID = 1113h and Vendor ID = 1013h)
Command and Status
Revision ID and Class Code
(Revision ID = ‘11100001’ and Class Code = 060700h)
Cache Line Size, Latency Timer, Header Type, and BIST
(Cache Line Size = 00h, Header Type = 82h, and BIST = 0h)
Memory Base Address
CardBus Status
PCI Bus Number, CardBus Number, Subordinate Bus
Number, and CardBus Latency Timer
Memory Base 0–1
Memory Limit 0–1
I/O Base 0–1
I/O Limit 0–1
Interrupt Line, Interrupt Pin, and Bridge Control
Subsystem Vendor ID and Subsystem Device ID
PC Card 16-Bit IF Legacy Mode Base Address
Reserved
Power Management Registers
Power Management Control and Status
DMA Slave Configuration Register
Socket Number
Configuration Miscellaneous 1
Memory Offset
00h
04h
08h
0Ch
10h
14h
18h
1Ch, 24h
20h, 28h
2Ch, 34h
30h, 38h
3Ch
40h
44h
48h—7Fh
80h
84h
90h
94h
98h
Page Number
48
49
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53
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55
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58
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66
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70
71
73
June 1998
ADVANCE DATA BOOK v0.3
47
PCI CONFIGURATION REGISTERS
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