CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Bit 3 — Special Cycle Enable
This bit reads back a ‘0’, since a PCI-to-PCI bridge cannot respond to special cycle transactions
as a target.
Bit 4 — Memory Write and Invalidate Enable
This bit reads back a ‘0’, since a PCI-to-PCI bridge cannot initiate a memory write and invalidate
command.
Bit 5 — Reserved
Bit 6 — Parity Error Check/Report Enable
This bit enables data parity-reporting-related circuitry, except for bit 31 of this register.
0
Data parity checking and reporting is disabled.
1
Data parity checking and reporting is enabled.
Bit 7 — Wait Cycle Control
This bit always reads ‘0’, indicating that the CL-PD6833 does not employ address or data stepping.
Bit 8 — System Error (SERR#) Enable
This bit enables the CL-PD6833 to report system errors by asserting the SERR# pin when address
parity errors occur. Bit 6 must also be set to ‘1’ to allow a data parity error to cause SERR#
activation. See also the description of bit 30 in this register.
0
Activation of SERR# on address parity error is disabled.
1
SERR# is activated whenever an address parity error is internally detected (slave mode).
Bits 19:9 — Reserved
Bit 20 — New Capabilities Present
A ‘1’ in this location indicates new capabilities in its configuration space (CardBus Controller and
Power Management capabilities). The CardBus Status register (offset 14h) is a pointer for these
capabilities. It defines the locations of the registers described under the new capabilities function.
Bits 23:21 — Fast Back-to-Back Capable, UDF Supported, and 66-MHz Supported
All of these features are not supported and read back ‘0’s.
Bit 24 — Master Data Parity Error Reported
This bit is set when a parity error is generated or detected, bit 6 of this register is set, and the
CL-PD6833 is acting as a bus master. To clear this bit, software must write a ‘1’ to it.
Bits 26:25 — DEVSEL# Timing
This field always reads back ‘01’, identifying the CL-PD6833 as a medium-speed device.
Bit 27 — Signalled Target Abort
To clear this bit, software must write a ‘1’ to it.
0
No target device has signalled a target abort.
1
A target device has signalled a target abort.
50
PCI CONFIGURATION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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