CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
15.3 AC Timing Specifications
This section includes system timing requirements for the CL-PD6833. Unless otherwise specified, timings
are provided in nanoseconds (ns), at TTL input levels, with the ambient temperature varying from 0°C to
70°C, and VCC varying from 3.0 V to 3.6 V, or 4.5 V to 5.5 V DC. The PCI bus speed is 33 MHz, unless
otherwise specified. Note the following conventions:
q A pound sign (#) at the end of a pin name indicates an active-low signal for the PCI bus.
q A dash (-) at the beginning of a pin name indicates an active-low signal for the PC Card (PCMCIA) bus.
q An asterisk (*) at the end of a pin name indicates an active-low signal that is a general interface for the
CL-PD6833.
Additionally, the following statements are true for all timing information:
q All timings assume a load of 50 pF.
q TTL signals are measured at TTL threshold; CMOS signals are measured at CMOS threshold.
Table 15-6. Index of AC Timing Specifications
Title
Table 15-7. FRAME#, AD[31:0], C/BE[3:0]#, and DEVSEL#
Table 15-8. TRDY# and STOP# Delay
Table 15-9. IDSEL Timing in a Configuration Cycle
Table 15-10. PAR Timing (PCI Bus)
Table 15-11. Pulse Mode Interrupt Timing
Table 15-12. Memory Read/Write Timing
Table 15-13. Word I/O Read/Write Timing
Table 15-14. PC Card (PCMCIA) Read/Write Timing when System is 8-Bit
Table 15-15. Normal Byte Read/Write Timing
Table 15-16. 16-Bit System to 8-Bit I/O Card (Odd Byte Timing)
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June 1998
ADVANCE DATA BOOK v0.3
ELECTRICAL SPECIFICATIONS
185
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