CL-PD6833
PCI-to-CardBus Host Adapter
15.3.1 PCI Bus Timing
Table 15-7. FRAME#, AD[31:0], C/BE[3:0]#, and DEVSEL#
Symbol
Parameter
t1
FRAME# setup to PCI_CLK
t2
AD[31:0] (address) setup to PCI_CLK
t3
AD[31:0] (address) hold from PCI_CLK
t4
AD[31:0] (data) setup to PCI_CLK
t5
AD[31:0] (data) active to High-Z from PCI_CLK
t6
C/BE[3:0]# (bus command) setup to PCI_CLK
t7
C/BE[3:0]# (bus command) hold from PCI_CLK
t8
C/BE[3:0]# (byte enable) setup to PCI_CLK
t9
DEVSEL# delay from PCI_CLK
t 10
DEVSEL# high before High-Z
PCI_VCC = 3.3 V PCI_VCC = 5.0 V
MIN MAX MIN MAX
7
–
7
–
7
–
7
–
0
–
0
–
7
–
7
–
0
28
0
28
7
–
7
–
0
–
0
–
7
–
7
–
–
11
–
11
1
–
1
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
PCI_CLK
186
ELECTRICAL SPECIFICATIONS
ADVANCE DATA BOOK v0.3
June 1998