CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Table 15-10. PAR Timing (PCI Bus)
Symbol
Parameter
t1
PAR setup to PCI_CLK (input to the CL-PD6833)
t2
PAR hold from PCI_CLK (input to the CL-PD6833)
t3
PAR valid delay from PCI_CLK (output from the CL-PD6833)
t4
PAR hold from PCI_CLK (output from the CL-PD6833)
MIN MAX Units
7
–
ns
0
–
ns
–
11
ns
0
–
ns
PCI_CLK
FRAME#
AD[31:0]
High-Z
Address
Data
C/BE[3:0]#
PAR
High-Z
Bus
Command
High-Z
Byte Enables
t1
t2
Address
& Command
Parity†
t3
t4
Data and
Byte Enable
Parity†
High-Z = high-impedance
† PAR goes high or low depending on AD[31:0] and C/BE[3:0]# values.
Figure 15-4. PAR Timing (PCI Bus)
190
ELECTRICAL SPECIFICATIONS
ADVANCE DATA BOOK v0.3
June 1998
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