CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
15.3.4 PC Card (PCMCIA) Bus Timing
Table 15-12. Memory Read/Write Timing
Symbol
Parameter
MIN
MAX
Units
t1
-REG, -CE[2:1], Address, and Write Data setup to Command (S × Tcp) − 10
active1
ns
t2
Command pulse width2
(C × Tcp) − 10
ns
t3
Address hold and Write Data valid from Command inactive3 (R × Tcp) − 10
ns
t4
-WAIT active from Command active
(C − 2) Tcp − 10
ns
t5
Command hold from -WAIT inactive
2 Tcp
ns
t6
Data setup before -OE inactive
(2 Tcp) + 10
ns
t7
Data hold after -OE inactive
0
ns
t8
Data valid from -WAIT inactive
Tcp + 10
ns
1 The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer
Set 0 default value of 00h, the setup time would be 20 ns. S = Nval + 1, see page 192.
2 The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 07h, the Command time would be 230 ns. C = Nval + 1, see page 192.
3 The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 04h, the hold (Recovery) time would be 170 ns. R = Nval + 1, see page 192.
-REG, -CE[2:1],
A[25:0]
-OE, -WE
-WAIT
D[15:0]
Write Cycle
D[15:0]
Read Cycle
t1
t2
t3
t5
t4
t6
t8
t7
Figure 15-6. Memory Read/Write Timing
June 1998
ADVANCE DATA BOOK v0.3
ELECTRICAL SPECIFICATIONS
193
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