CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Table 15-15. Normal Byte Read/Write Timing
Symbol
Parameter
MIN
MAX
Units
t1
Address setup to Command active1
(S × Tcp) – 10
ns
t2
Command pulse width2
(C × Tcp) – 10
ns
t3
Address hold from Command inactive3
(R × Tcp) – 10
ns
1 The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer
Set 0 default value of 00h, the setup time would be 20 ns. S = Nval + 1, see page 192.
2 The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 07h, the Command time would be 230 ns. C = Nval + 1, see page 192.
3 The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 04h, the hold (Recovery) time would be 170 ns. R = Nval + 1, see page 192.
-REG,
A[25:0]
t1
t3
t2
-IOWR, -IORD,
-OE, -WE
-CE1
-CE2
D[7:0]
Write Cycle
Odd/Even Data
D[7:0]
Read Cycle
D[15:8]
Read or
Write Cycle
Odd/Even Data
XX
NOTE: This is the normal byte read/write timing for all other byte
accesses, including odd I/O cycles where -IOIS16 is low.
Figure 15-9. Normal Byte Read/Write Timing
June 1998
ADVANCE DATA BOOK v0.3
ELECTRICAL SPECIFICATIONS
197
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