CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.19
Configuration Miscellaneous 1
Register Name: Configuration Miscellaneous 1
Offset: 98h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Register Per: socket
Bit 25
Bit 24
Byte 3
Bit 23
Bit 22
Bit 21
Reserved
R:00000000
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Byte 2
Reserved
Byte 1
Byte 0
Bit 15
Bit 7
Bit 14
Bit 6
Bit 13
Reserved
R:000000
Bit 5
Reserved
R:00000
R:00000000
Bit 12
Bit 11
Bit 4
Bit 3
Bit 10
Bit 9
Bit 8
D3 Disable
Auto Reset —
PME_CXT
R/W:0
Bit 2
Disable
Master
Prefetch
R/W:0
Bit 1
Pin Mapping
Lock
R/W:0
Bit 0
Enable
INTA#, INTB#
in PCI/Way
Management
Enable
R/W:0
R/W:0
Subsystem
Vendor ID
Lock
R/W:0
Bit 0 — Subsystem Vendor ID Lock
This bit defaults to ‘0’. When this bit is set to ‘1’, the Subsystem Vendor ID and Subsystem
Device ID registers (memory offset 40h) become read only. This register is per chip.
Bit 1 — Management Enable
This bit is used to control the routing of management interrupts to the ISA IRQ or PCI INT pin. This
is used only when the CL-PD6833 is programmed for non-PCI style interrupts.
0
Management interrupts are routed to the INT pin indicated by the Interrupt Pin register (memory offset
3Dh): INTA# for Socket A and INTB# for Socket B.
1
Management interrupts are routed to the ISA IRQ line (IRQ3, 4, 5, 7, 11, 12, 14, or 15) as indicated by
the Management Interrupt Configuration register (memory offset 805h).
Bit 2 — Enable INTA#, INTB# in PCI/Way
This register is per chip.
0
PCI/Way data stream is compatible with the CL-PD6832.
1
INTA# and INTB# are included in the PCI/Way data stream.
Bits 7:3 — Reserved
Bit 8 — Pin Mapping Lock
This bit determines the PCI memory space 914h–915h pin mapping register accessibility. (Bit
position is R/W for each socket: chip-level function, programmable in function 0 only.)
0
Pin mapping can be programmed in register 914–915h.
1
Write access to register 914–915h is disabled.
June 1998
ADVANCE DATA BOOK v0.3
73
PCI CONFIGURATION REGISTERS
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